1. Field of the Invention
The present invention relates to a semiconductor lead frame using tin in which the formation of whiskers is reduced by reducing a grain size, a semiconductor package having the lead frame, and a method of plating the lead frame.
2. Description of the Related Art
Conventionally, a semiconductor lead frame is a core component of a semiconductor package that connects inner components of the semiconductor package to external terminals. Semiconductor lead frames are formed in various shapes and structures through stamping processes or etching processes and are used to form semiconductor packages with other components such as semiconductor chips.
A semiconductor lead frame includes a die pad, on which semiconductor chips are mounted. The die pad is formed on a center of a substrate and the corners of the die pad are supported by tie bars. A plurality of inner leads is adjacently connected by a dambar. A plurality of outer leads are disposed on the opposite side of the dambar from the inner leads so that the outer leads can be connected to external terminals when the semiconductor package is fabricated. Also, a wire bonding region for connecting each terminal of a semiconductor chip to be mounted is formed at ends of the inner leads.
The outer leads of the lead frame must be solder wettable and anti-corrosive to facilitate soldering with external terminals since the outer leads are directly electrically connected to external terminals. To attain solder wettability, a soldering base composed of an alloy of Sn and Pb is plated on a predetermined region of the outer leads.
However, recently, the Sn—Pb alloy has been replaced by pure Sn since Pb can not be used due to environmental regulations. One of the problems of plating Sn on a semiconductor lead frame is the generation of whiskers. The whiskers are tin single crystals having a length of a few millimeters and a width of 1-5 micrometers in the shape of a beard. Due to the growth of the whiskers, disconnections of the lead frame from external terminals can occur or, due to broken pieces of the whiskers, malfunctions of electronic components can occur.
A method of minimizing whiskers by implanting ions of Pb, Bi, Sb, Ti, Cu, Ag, Au, and Cd in the Sn plating is disclosed in U.S. Pat. No. 5,393,573. A method of minimizing the whiskers in a Sn or Sn alloy plating layer by controlling an angle of crystal face to 5-22° is disclosed in U.S. Patent Publication No. 2003-0226758. A method of minimizing the whiskers in a Sn or Sn alloy plating layer by controlling tensile strength of the plating layer is disclosed in U.S. Patent Publication No. 2003-0025182. Also, a method of minimizing the whiskers in a Sn plating layer by forming an underlying plating is disclosed in U.S. Patent Publication No. 2002-0187364.
FIG. 1 is a schematic diagram illustrating how a whisker 130 is generated when a Sn plating layer 120 is formed on a substrate 110 formed of Cu.
Referring to FIG. 1, it is assumed that the whisker 130 is formed on the substrate 110 composed of Cu by internal stress when the Sn plating layer 120 is formed. At room temperature, the diffusion of atoms occurs through grain boundaries than the inner part of the grain. The diffusion speed of Cu atoms forming the substrate 110 is greater than the diffusion speed of Sn atoms for plating. Therefore, a copper-tin inter-metal compound Cu6Sn5 is formed at a grain boundary between the substrate 110 and the Sn plating layer since the Cu atoms preferentially diffuse to the Sn grain boundary of the plating layer. Therefore, the volume of the grain boundary expands by approximately 45%. As a result, the whisker 130 is grown by the compression stress applied to the grains.
Conventionally, to reduce the whiskers 130, the formation of a diffusion barrier layer to prevent the preferential diffusion of the Cu atoms into the grain boundary at room temperature through an annealing process, an underlying plating process, or a reflow process; the lowering of fraction of a grain boundary that provides the path of the preferential diffusion; the reduction of a diffusion capability of the grain boundary; and the reduction of the overall compression stress generated at the grain boundary between the plated layer and the substrate have been studied.
FIG. 2 is a schematic diagram illustrating how whiskers are generated when a Sn plated layer is formed on a substrate 210 formed of alloy 42 (Fe-42% Ni).
Referring to FIG. 2, when the Sn plated layer 220 is formed on the substrate 210 formed of an alloy of Fe—Ni, whiskers are generated by differences in the thermal expansion rates between the Sn plated layer 220 and the substrate 210. When a temperature cycle is applied to the Sn plated layer 220 and the substrate 210, compression stress at a high temperature is applied at a grain boundary between the Sn plated layer 220 and the substrate 210, and whiskers are grown when the temperature cycle is continually applied. Conventional methods of reducing whiskers when a Cu substrate is used are not effective since the mechanism of generating the whiskers is different from the mechanism resulting from the Cu substrate.
Also, if additional processes, such as an annealing process, an underlying plating process, or a reflow process are included to reduce the whisker, the overall process time increases and the process management is complicated, thereby increasing the manufacturing costs.
Moreover, to provide plating with a coarse grain size or aligned grains, process conditions must be strictly controlled.
Conventionally, to achieve a plating thickness of 10 micrometers, the plating must be performed for 60 seconds at 20 ampere per square deci-meter (ASD). However, in the case of a Sn pre-plated lead frame, to meet this plating condition, the overall length of the plating equipment must be great or the plating speed must be half of normal conventional plating speeds.